Fabrication of via-chain test structures for 3D IC technology using dielectric glue bonding on 200 mm wafers

We developed a four-layer mask set of via-chain test structures to evaluate process feasibility of monolithic three-dimensional (3D) wafer-scale integrated circuitry (IC) technology using wafer bonding with dielectric polymers on a 200 mm wafer platform. The experimental results achieved to-date are presented for four main processes: (1) precise wafer alignment of 200 mm wafer; (2) evaluation of various dielectric glue materials for wafer bonding; (3) precision wafer thinning and planarization of the top wafer after bonding; and (4) formation of inter-chip interconnects using high-aspect-ratio copper damascene patterning technology. Various fabrication challenges are discussed, particularly the wafer bonding integrity and the compatibility with current semiconductor fabrication protocols. This 3D integration technology offers the potential of significant improvement in interconnect performance, high functionality for heterogeneous integration, high packaging density and lower overall manufacturing cost.