Flash translation layer for solid state drives

Ilhoon Shin

doi:10.1007/978-3-642-27314-8_58

Flash translation layer for solid state drives

Ilhoon Shin

Electronic Engineering Program

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Solid State Drives organize NAND flash memory in m-way & n-channel structure in order to increase the read/write throughput and the capacity. In m-way & n-channel structure, the basic read/write unit is usually multiples of physical page size. However, the influence of the read/write unit size on the performance has not been sufficiently studied. In this work, we investigate the influence of the read/write unit size on the representative FTL schemes. The results through a trace-driven simulation show that the optimal point is in the middle of small unit and large unit. Too large read/write unit hurts the performance seriously because small sized write requests occupy a considerable portion in windows PC. Especially, the performance of the page mapping scheme steeply decreases by large clustered page when the utilization is high.

Original language	English
Title of host publication	Future Communication, Computing, Control and Management
Pages	431-437
Number of pages	7
Edition	VOL. 2
DOIs	https://doi.org/10.1007/978-3-642-27314-8_58
State	Published - 2012
Event	2011 International Conference on Future Communication, Computing, Control and Management, ICF4C 2011 - Phuket, Thailand Duration: 16 Dec 2011 → 17 Dec 2011

Publication series

Name	Lecture Notes in Electrical Engineering
Number	VOL. 2
Volume	142 LNEE
ISSN (Print)	1876-1100
ISSN (Electronic)	1876-1119

Conference

Conference	2011 International Conference on Future Communication, Computing, Control and Management, ICF4C 2011
Country/Territory	Thailand
City	Phuket
Period	16/12/11 → 17/12/11

Keywords

clustered page
flash translation layer
NAND flash memory
Solid State Drives

Access to Document

10.1007/978-3-642-27314-8_58

Cite this

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title = "Flash translation layer for solid state drives",

abstract = "Solid State Drives organize NAND flash memory in m-way \& n-channel structure in order to increase the read/write throughput and the capacity. In m-way \& n-channel structure, the basic read/write unit is usually multiples of physical page size. However, the influence of the read/write unit size on the performance has not been sufficiently studied. In this work, we investigate the influence of the read/write unit size on the representative FTL schemes. The results through a trace-driven simulation show that the optimal point is in the middle of small unit and large unit. Too large read/write unit hurts the performance seriously because small sized write requests occupy a considerable portion in windows PC. Especially, the performance of the page mapping scheme steeply decreases by large clustered page when the utilization is high.",

keywords = "clustered page, flash translation layer, NAND flash memory, Solid State Drives",

author = "Ilhoon Shin",

year = "2012",

doi = "10.1007/978-3-642-27314-8\_58",

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series = "Lecture Notes in Electrical Engineering",

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}

Shin, I 2012, Flash translation layer for solid state drives. in Future Communication, Computing, Control and Management. VOL. 2 edn, Lecture Notes in Electrical Engineering, no. VOL. 2, vol. 142 LNEE, pp. 431-437, 2011 International Conference on Future Communication, Computing, Control and Management, ICF4C 2011, Phuket, Thailand, 16/12/11. https://doi.org/10.1007/978-3-642-27314-8_58

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AU - Shin, Ilhoon

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N2 - Solid State Drives organize NAND flash memory in m-way & n-channel structure in order to increase the read/write throughput and the capacity. In m-way & n-channel structure, the basic read/write unit is usually multiples of physical page size. However, the influence of the read/write unit size on the performance has not been sufficiently studied. In this work, we investigate the influence of the read/write unit size on the representative FTL schemes. The results through a trace-driven simulation show that the optimal point is in the middle of small unit and large unit. Too large read/write unit hurts the performance seriously because small sized write requests occupy a considerable portion in windows PC. Especially, the performance of the page mapping scheme steeply decreases by large clustered page when the utilization is high.

AB - Solid State Drives organize NAND flash memory in m-way & n-channel structure in order to increase the read/write throughput and the capacity. In m-way & n-channel structure, the basic read/write unit is usually multiples of physical page size. However, the influence of the read/write unit size on the performance has not been sufficiently studied. In this work, we investigate the influence of the read/write unit size on the representative FTL schemes. The results through a trace-driven simulation show that the optimal point is in the middle of small unit and large unit. Too large read/write unit hurts the performance seriously because small sized write requests occupy a considerable portion in windows PC. Especially, the performance of the page mapping scheme steeply decreases by large clustered page when the utilization is high.

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KW - flash translation layer

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KW - Solid State Drives

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Y2 - 16 December 2011 through 17 December 2011

ER -

Flash translation layer for solid state drives

Abstract

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Keywords

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