@inproceedings{49ba16b92dac49b98275ffd4c08fa2e4,
title = "Gated-thyristor DRAM cell with pillar channel structure",
abstract = "In this work, a DRAM cell based on gated-thyristor having pillar channel and sidewall gate is proposed and investigated through device simulation study. Stored electrons in the base region make a difference in read current lowering potential barrier. It has a fast writing speed under 10 ns because of its mechanism based on thermal injection and highly scalable structure because of self-connected word line.",
author = "Hyungjin Kim and Kwon, \{Min Woo\} and Baek, \{Myung Hyun\} and Sungmin Hwang and Sihyun Kim and Taejin Jang and Lee, \{Jeong Jun\} and Kim, \{Hyun Min\} and Kitae Lee and Park, \{Byung Gook\}",
note = "Publisher Copyright: {\textcopyright} 2017 JSAP.; 22nd Silicon Nanoelectronics Workshop, SNW 2017 ; Conference date: 04-06-2017 Through 05-06-2017",
year = "2017",
month = dec,
day = "29",
doi = "10.23919/SNW.2017.8242302",
language = "English",
series = "2017 Silicon Nanoelectronics Workshop, SNW 2017",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "71--72",
booktitle = "2017 Silicon Nanoelectronics Workshop, SNW 2017",
}