TY - JOUR
T1 - Gated twin-bit silicon-oxide-nitride-oxide-silicon NAND flash memory for high-density nonvolatile memory
AU - Kim, Yoon
AU - Shim, Won Bo
AU - Park, Byung Gook
N1 - Publisher Copyright:
© 2015 The Japan Society of Applied Physics.
PY - 2015/6/1
Y1 - 2015/6/1
N2 - In this paper, we report the fabrication and analysis of the gated twin-bit NAND flash memory with a nitride charge-trapping layer. This device is based on the recessed channel structure, and it has an additional cut-off gate that enables 2-bit operation. Therefore, the density of the array can be doubled without any difficulty in patterning. The fabrication method for gated twin-bit (GTB) silicon-oxide-nitride-oxide-silicon (SONOS) memories and their electrical characteristics are described in this paper. Program/erase characteristics are observed and the 2-bit operation is verified by the forward-reverse reading scheme.
AB - In this paper, we report the fabrication and analysis of the gated twin-bit NAND flash memory with a nitride charge-trapping layer. This device is based on the recessed channel structure, and it has an additional cut-off gate that enables 2-bit operation. Therefore, the density of the array can be doubled without any difficulty in patterning. The fabrication method for gated twin-bit (GTB) silicon-oxide-nitride-oxide-silicon (SONOS) memories and their electrical characteristics are described in this paper. Program/erase characteristics are observed and the 2-bit operation is verified by the forward-reverse reading scheme.
UR - http://www.scopus.com/inward/record.url?scp=84930430005&partnerID=8YFLogxK
U2 - 10.7567/JJAP.54.064201
DO - 10.7567/JJAP.54.064201
M3 - Article
AN - SCOPUS:84930430005
SN - 0021-4922
VL - 54
JO - Japanese Journal of Applied Physics
JF - Japanese Journal of Applied Physics
IS - 6
M1 - 064201
ER -