Abstract
This article proposes a fundamental frequency oscillator topology that efficiently extracts maximum power from the transistors while minimizing the effective parasitic capacitance, leading to a further increase in output power by enabling the adoption of larger size transistors. High-power fundamental oscillators operating at 150 and 245 GHz are designed using the proposed topology. Implemented in a 40-nm CMOS technology, the proposed 150- and 245-GHz oscillators achieve a peak output power of 12.1 and -2.54 dBm, a peak dc-to-RF efficiency of 14.3% and 1.2%, and a phase noise at 1 MHz of -98.2 and -86.3 dBc/Hz, respectively. The corresponding figure-of-merit (FoM/FoMA) values of the proposed 150- and 245-GHz oscillators are -193/-202 and -175/-186 dBc/Hz, respectively.
| Original language | English |
|---|---|
| Pages (from-to) | 3683-3693 |
| Number of pages | 11 |
| Journal | IEEE Journal of Solid-State Circuits |
| Volume | 59 |
| Issue number | 11 |
| DOIs | |
| State | Published - 2024 |
Keywords
- Beamforming
- CMOS
- high-power oscillator
- phased array transceivers
- power-combining
- sub-THz source
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