Abstract
This brief proposes a high-power harmonic oscillator topology that adopts a series LC resonant feedback network to minimize the effective parasitic capacitance of the oscillator at the fundamental frequency while increasing the output power at the second harmonic by enabling a larger transistor size and minimizing the common-mode output conductance. Implemented in the 28-nm CMOS technology, the proposed 270-GHz oscillator achieves a peak output power of −3.2 dBm, a peak dc-to-RF efficiency of 0.81% and phase noise values of −56.8, −84.68 and −90.12 dBc/Hz at 100 kHz, 1 MHz and 10 MHz offsets, respectively.
| Original language | English |
|---|---|
| Pages (from-to) | 668-672 |
| Number of pages | 5 |
| Journal | IEEE Transactions on Circuits and Systems II: Express Briefs |
| Volume | 72 |
| Issue number | 5 |
| DOIs | |
| State | Published - 2025 |
Keywords
- harmonic oscillator
- mm-wave
- output power optimization
- push-push oscillator
- Sub-THz