Higher-k dielectrics and conductive oxide electrodes for next generation DRAMs with a design rule of 20 nm ^#

Dynamic random access memory (DRAM) is used as the main memory in every personal computer, due to its high density, high speed and efficient memory function. The ever-shrinking dimensions of DRAM cells with increasing packing density made the cell's capacitor size to be smaller. For successful operation of DRAM, a large cell capacitance ( 25 fF) and low leakage current (10 ⁷ A/cm ² or 1 fA/cell) are required. In a traditional Si-based capacitor, the target cell capacitance has been achieved by increasing the surface area of the capacitor. More recently, innovations have been made by development of the component materials. A metal electrode, TiN or Ru, and a dielectric material with a moderate-k value (k is the relative dielectric constant), such as HfO ₂ (k 25) and ZrO ₂ (k 40), are being explored in giga-bit scale DRAMs. The minimum achievable t _ox is 0.7 nm for ZrO ₂ which is being used currently in DRAM industry. However, the technology road map for memory devices states that t _ox of less than 0.45 nm is necessary for the DRAMs with a design rule of 20 nm. Perovskite-based dielectric films such as SrTiO ₃ (STO) and (Ba, Sr)TiO ₃ were reported to exhibit k values of several hundreds. However, growth of these films showed very slow growth rate and much more complicated processes than growth of binary oxide with the atomic layer deposition (ALD) technique which is a method of choice for the growth of the dielectric films and electrodes in microelectronic devices. Therefore, material and process innovations are necessary for next generation DRAM capacitors.