TY - GEN
T1 - Implementing triple adjacent Error Correction in double error correction Orthogonal Latin Squares Codes
AU - Reviriego, P.
AU - Liu, S.
AU - Maestro, J. A.
AU - Lee, S.
AU - Touba, N. A.
AU - Datta, R.
PY - 2013
Y1 - 2013
N2 - Soft errors have been a concern in memories for many years. In older technologies, soft errors typically affected a single memory cell but as technology scaled, Multiple Cell Upsets (MCUs) that affect a group of nearby cells have become more common. This trend is expected to continue making MCUs more frequent and also increasing the number of cells affected. To avoid data corruption in memories, Error Correction Codes (ECCs) are used. Single Error Correction (SEC) codes that can correct one bit error per word are effective only against single errors. To protect against MCUs, one option is to use more sophisticated error correction codes like for example, Orthogonal Latin Squares Codes (OLSC). In this paper, a modification of the OLSC decoding algorithm is proposed for codes that can correct two random errors. This modification has little impact on circuit complexity and enables triple adjacent error correction which is interesting when MCUs are present.
AB - Soft errors have been a concern in memories for many years. In older technologies, soft errors typically affected a single memory cell but as technology scaled, Multiple Cell Upsets (MCUs) that affect a group of nearby cells have become more common. This trend is expected to continue making MCUs more frequent and also increasing the number of cells affected. To avoid data corruption in memories, Error Correction Codes (ECCs) are used. Single Error Correction (SEC) codes that can correct one bit error per word are effective only against single errors. To protect against MCUs, one option is to use more sophisticated error correction codes like for example, Orthogonal Latin Squares Codes (OLSC). In this paper, a modification of the OLSC decoding algorithm is proposed for codes that can correct two random errors. This modification has little impact on circuit complexity and enables triple adjacent error correction which is interesting when MCUs are present.
KW - Error correction codes
KW - Multiple Cell Upsets (MCUs)
KW - majority logic decoding
KW - memory
UR - http://www.scopus.com/inward/record.url?scp=84891315844&partnerID=8YFLogxK
U2 - 10.1109/DFT.2013.6653601
DO - 10.1109/DFT.2013.6653601
M3 - Conference contribution
AN - SCOPUS:84891315844
SN - 9781479915835
T3 - Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
SP - 167
EP - 171
BT - Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2013
T2 - 2013 26th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2013
Y2 - 2 October 2013 through 4 October 2013
ER -