Abstract
This work presents an in-memory computing architecture based on positive feedback field-effect transistors integrated in a NAND Flash-like array. The proposed system performs complete Boolean logic operations—including XOR and XNOR—directly within the memory array without requiring external circuits. A selective write mechanism combining pre-conditioning with hot carrier injection is introduced to ensure reliable data storage regardless of current flow conditions. The feedback field-effect transistor-based design offers high functional density and scalability, making it a promising candidate for energy-efficient logic-in-memory and neuromorphic computing applications.
| Original language | English |
|---|---|
| Article number | 01SP10 |
| Journal | Japanese Journal of Applied Physics |
| Volume | 65 |
| Issue number | 1 |
| DOIs | |
| State | Published - 14 Jan 2026 |
Keywords
- charge trap layer
- in-memory computation
- positive feedback field effect transistor
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