Innovative 3-D n-Capacitor-Stacked FeRAM With V_DD/3 Inhibition Scheme and Cell Design for Nonvolatile DRAM Applications

This work proposes a novel 3-D n-capacitor-stacked (nCS) ferroelectric random access memory (FeRAM) architecture that enhances cell capacitance and memory density while addressing key limitations of conventional 1T-1C and 1T-nC FeRAM designs. By integrating horizontally oriented/vertically stacked ferroelectric (FE) capacitors on a single transistor, the architecture achieves higher storage capacity within the same footprint without compromising read performance. Calibrated TCAD simulations show that an eight-capacitor-stacked FeRAM with a bitline (BL) capacitance (C_BL) of 17 fF exhibits superior sensing margin compared with a four-capacitor-stacked counterpart with a C_BL of 34 fF, indicating that increasing the number of stacked capacitors minimally impacts parasitic BL capacitance-unlike conventional approaches that expand array size. To ensure reliable 1T-nC array operation, an inhibition bias scheme is experimentally validated, effectively mitigating polarization loss in unselected cells and maintaining a sufficient sensing margin. Moreover, an optimized 4F² memory array layout is proposed, leveraging the stackable structure while maintaining compatibility with existing fabrication processes and achieving excellent area efficiency. The results confirm that the proposed 3-D nCS FeRAM architecture enables high-density, energy-efficient memory integration, providing a promising pathway toward next-generation artificial intelligence (AI) and embedded memory applications.