TY - GEN
T1 - Investigation of Cu-to-Cu and Oxide-to-Oxide Bonding
AU - Lee, Sangmin
AU - Oh, Gwangsik
AU - Choi, Junyoung
AU - Kim, Yoonho
AU - Park, Sangwoo
AU - Kim, Sarah Eunkyung
N1 - Publisher Copyright:
© 2023 IEEE.
PY - 2023
Y1 - 2023
N2 - While device scaling of planar devices faces physical limitations, vertically stacked devices are becoming more important due to package miniaturization, cost reduction and enhanced functionality. 3D packaging technology improves performance and electrical signal and power integrities, and becomes a key packaging technology for the next generation heterogeneous integration. We demonstrated both Cu-Cu bonding and SiO2-SiO2 bonding at 300°C under the 700 kPa using the two step Ar-N2 plasma treatment process prior to bonding. Currently, it is difficult to fabricate Cu/SiO2 hybrid bonded specimens in our laboratory, so Cu bonding and oxide bonding were investigated separately in this experiment. The effect of two-step Ar-N2plasma treatment process on both Cu and SiO2 surface was studied using XPS (X-ray photoelectron spectroscopy). A 3-4 nm copper nitride (Cu4N) layer was formed on the copper surface to prevent additional Cu oxidation, and some Si-O bonds were broken on the oxide surface to form NSi3and NSiO2. After the plasma treatments, Cu-Cu bonding and oxide-to-oxide bonding were carried out separately. According to the bonded interface measurements by SAT (scanning acoustic tomography), the Cu-Cu bonded interface was excellent, while the SiO2-SiO2 bonded interface showed very fine voids even though the RMS roughness was 0.092 nm. In addition, the particle removal process in a wafer dicing process was evaluated with a positive photoresist for die-to-wafer bonding. In addition, for die-to-wafer bonding, it is necessary to remove particles generated in the wafer dicing process, and for this purpose, a positive photoresist coating process was evaluated.
AB - While device scaling of planar devices faces physical limitations, vertically stacked devices are becoming more important due to package miniaturization, cost reduction and enhanced functionality. 3D packaging technology improves performance and electrical signal and power integrities, and becomes a key packaging technology for the next generation heterogeneous integration. We demonstrated both Cu-Cu bonding and SiO2-SiO2 bonding at 300°C under the 700 kPa using the two step Ar-N2 plasma treatment process prior to bonding. Currently, it is difficult to fabricate Cu/SiO2 hybrid bonded specimens in our laboratory, so Cu bonding and oxide bonding were investigated separately in this experiment. The effect of two-step Ar-N2plasma treatment process on both Cu and SiO2 surface was studied using XPS (X-ray photoelectron spectroscopy). A 3-4 nm copper nitride (Cu4N) layer was formed on the copper surface to prevent additional Cu oxidation, and some Si-O bonds were broken on the oxide surface to form NSi3and NSiO2. After the plasma treatments, Cu-Cu bonding and oxide-to-oxide bonding were carried out separately. According to the bonded interface measurements by SAT (scanning acoustic tomography), the Cu-Cu bonded interface was excellent, while the SiO2-SiO2 bonded interface showed very fine voids even though the RMS roughness was 0.092 nm. In addition, the particle removal process in a wafer dicing process was evaluated with a positive photoresist for die-to-wafer bonding. In addition, for die-to-wafer bonding, it is necessary to remove particles generated in the wafer dicing process, and for this purpose, a positive photoresist coating process was evaluated.
KW - 3D packaging
KW - Copper nitride passivation
KW - Cu bonding
KW - Heterogeneous packaging
KW - Oxide bonding
KW - Two-step plasma treatment
UR - http://www.scopus.com/inward/record.url?scp=85168307960&partnerID=8YFLogxK
U2 - 10.1109/ECTC51909.2023.00258
DO - 10.1109/ECTC51909.2023.00258
M3 - Conference contribution
AN - SCOPUS:85168307960
T3 - Proceedings - Electronic Components and Technology Conference
SP - 1519
EP - 1523
BT - Proceedings - IEEE 73rd Electronic Components and Technology Conference, ECTC 2023
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 73rd IEEE Electronic Components and Technology Conference, ECTC 2023
Y2 - 30 May 2023 through 2 June 2023
ER -