Investigation on Variability of Ferroelectric-Gate Field-Effect Transistor Memory by Random Spatial Distribution of Interface Trap

Kitae Lee; Sihyun Kim; Munhyeon Kim; Jong Ho Lee; Byung Gook Park; Daewoong Kwon

doi:10.1109/TNANO.2022.3207505

Investigation on Variability of Ferroelectric-Gate Field-Effect Transistor Memory by Random Spatial Distribution of Interface Trap

Kitae Lee, Sihyun Kim, Munhyeon Kim, Jong Ho Lee, Byung Gook Park, Daewoong Kwon

Dept. of Electrical and Information Engineering

Research output: Contribution to journal › Article › peer-review

4 Scopus citations

Abstract

We investigated the variability of memory window (MW) in ferroelectric-gate field-effect transistor (FeFET) by considering the spatial distribution of the trap density at the ferroelectric layer/interfacial layer (FE/IL) interface. Through technology computer-aided design (TCAD) simulations including calibrated ferroelectric parameters, the variability of ultrathin body (UTB) structured FeFETs by the scaling of IL and channel area was confirmed. It was revealed that the reduction of IL thickness (TIL) not only increases mean of MW (μMW) but also decreases standard deviation of MW (σMW). Additionally, by identifying the σMW/μMW sensitivity for the reduction of gate length (LG) and channel width (W), it was indicated that W causes the more serious σMW degradation because short channel effects by LG scaling mitigate the σMW degradation.

Original language	English
Pages (from-to)	534-538
Number of pages	5
Journal	IEEE Transactions on Nanotechnology
Volume	21
DOIs	https://doi.org/10.1109/TNANO.2022.3207505
State	Published - 2022

Keywords

ferroelectric variation
Ferroelectric-gate FET (FeFET)
interface trap
random spatial distribution
variability

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10.1109/TNANO.2022.3207505

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title = "Investigation on Variability of Ferroelectric-Gate Field-Effect Transistor Memory by Random Spatial Distribution of Interface Trap",

abstract = "We investigated the variability of memory window (MW) in ferroelectric-gate field-effect transistor (FeFET) by considering the spatial distribution of the trap density at the ferroelectric layer/interfacial layer (FE/IL) interface. Through technology computer-aided design (TCAD) simulations including calibrated ferroelectric parameters, the variability of ultrathin body (UTB) structured FeFETs by the scaling of IL and channel area was confirmed. It was revealed that the reduction of IL thickness (TIL) not only increases mean of MW (μMW) but also decreases standard deviation of MW (σMW). Additionally, by identifying the σMW/μMW sensitivity for the reduction of gate length (LG) and channel width (W), it was indicated that W causes the more serious σMW degradation because short channel effects by LG scaling mitigate the σMW degradation.",

keywords = "ferroelectric variation, Ferroelectric-gate FET (FeFET), interface trap, random spatial distribution, variability",

author = "Kitae Lee and Sihyun Kim and Munhyeon Kim and Lee, \{Jong Ho\} and Park, \{Byung Gook\} and Daewoong Kwon",

note = "Publisher Copyright: {\textcopyright} 2002-2012 IEEE.",

year = "2022",

doi = "10.1109/TNANO.2022.3207505",

language = "English",

volume = "21",

pages = "534--538",

journal = "IEEE Transactions on Nanotechnology",

issn = "1536-125X",

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TY - JOUR

T1 - Investigation on Variability of Ferroelectric-Gate Field-Effect Transistor Memory by Random Spatial Distribution of Interface Trap

AU - Lee, Kitae

AU - Kim, Sihyun

AU - Kim, Munhyeon

AU - Lee, Jong Ho

AU - Park, Byung Gook

AU - Kwon, Daewoong

PY - 2022

Y1 - 2022

N2 - We investigated the variability of memory window (MW) in ferroelectric-gate field-effect transistor (FeFET) by considering the spatial distribution of the trap density at the ferroelectric layer/interfacial layer (FE/IL) interface. Through technology computer-aided design (TCAD) simulations including calibrated ferroelectric parameters, the variability of ultrathin body (UTB) structured FeFETs by the scaling of IL and channel area was confirmed. It was revealed that the reduction of IL thickness (TIL) not only increases mean of MW (μMW) but also decreases standard deviation of MW (σMW). Additionally, by identifying the σMW/μMW sensitivity for the reduction of gate length (LG) and channel width (W), it was indicated that W causes the more serious σMW degradation because short channel effects by LG scaling mitigate the σMW degradation.

AB - We investigated the variability of memory window (MW) in ferroelectric-gate field-effect transistor (FeFET) by considering the spatial distribution of the trap density at the ferroelectric layer/interfacial layer (FE/IL) interface. Through technology computer-aided design (TCAD) simulations including calibrated ferroelectric parameters, the variability of ultrathin body (UTB) structured FeFETs by the scaling of IL and channel area was confirmed. It was revealed that the reduction of IL thickness (TIL) not only increases mean of MW (μMW) but also decreases standard deviation of MW (σMW). Additionally, by identifying the σMW/μMW sensitivity for the reduction of gate length (LG) and channel width (W), it was indicated that W causes the more serious σMW degradation because short channel effects by LG scaling mitigate the σMW degradation.

KW - ferroelectric variation

KW - Ferroelectric-gate FET (FeFET)

KW - interface trap

KW - random spatial distribution

KW - variability

UR - https://www.scopus.com/pages/publications/85139412417

U2 - 10.1109/TNANO.2022.3207505

DO - 10.1109/TNANO.2022.3207505

M3 - Article

AN - SCOPUS:85139412417

SN - 1536-125X

VL - 21

SP - 534

EP - 538

JO - IEEE Transactions on Nanotechnology

JF - IEEE Transactions on Nanotechnology

ER -

Investigation on Variability of Ferroelectric-Gate Field-Effect Transistor Memory by Random Spatial Distribution of Interface Trap

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Keywords

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