Low-power, resilient interconnection with orthogonal latin squares

Seung Eun Lee; Wei Wu; Ravi Iyer; Yoon Seok Yang; Gwan S. Choi

doi:10.1109/MDT.2011.35

Low-power, resilient interconnection with orthogonal latin squares

Seung Eun Lee
, Wei Wu
, Ravi Iyer
, Yoon Seok Yang
, Gwan S. Choi

Electronic Engineering Program

Research output: Contribution to journal › Article › peer-review

17 Scopus citations

Abstract

A reliable, energy-efficient on-chip interconnection network employing low-swing signaling can be designed by incorporating error-correcting code. Orthogonal Latin Square Code (OLSC) can protect the interconnection against transient errors, while also lowering energy consumption. When applied to a 64-bit link using a 45-nm CMOS technology with low-swing signaling, OLSC provided up to 55 energy reduction, with only a small area overhead and no loss in reliability.

Original language	English
Article number	5739839
Pages (from-to)	30-38
Number of pages	9
Journal	IEEE Design and Test of Computers
Volume	28
Issue number	2
DOIs	https://doi.org/10.1109/MDT.2011.35
State	Published - Mar 2011

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

design and test
ECC
error-correcting code
OLSC
on-chip interconnection
orthogonal Latin square
resilience and low power design

Access to Document

10.1109/MDT.2011.35

Cite this

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title = "Low-power, resilient interconnection with orthogonal latin squares",

abstract = "A reliable, energy-efficient on-chip interconnection network employing low-swing signaling can be designed by incorporating error-correcting code. Orthogonal Latin Square Code (OLSC) can protect the interconnection against transient errors, while also lowering energy consumption. When applied to a 64-bit link using a 45-nm CMOS technology with low-swing signaling, OLSC provided up to 55 energy reduction, with only a small area overhead and no loss in reliability.",

keywords = "design and test, ECC, error-correcting code, OLSC, on-chip interconnection, orthogonal Latin square, resilience and low power design",

author = "Lee, \{Seung Eun\} and Wei Wu and Ravi Iyer and Yang, \{Yoon Seok\} and Choi, \{Gwan S.\}",

year = "2011",

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language = "English",

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AU - Wu, Wei

AU - Iyer, Ravi

AU - Yang, Yoon Seok

AU - Choi, Gwan S.

PY - 2011/3

Y1 - 2011/3

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AB - A reliable, energy-efficient on-chip interconnection network employing low-swing signaling can be designed by incorporating error-correcting code. Orthogonal Latin Square Code (OLSC) can protect the interconnection against transient errors, while also lowering energy consumption. When applied to a 64-bit link using a 45-nm CMOS technology with low-swing signaling, OLSC provided up to 55 energy reduction, with only a small area overhead and no loss in reliability.

KW - design and test

KW - ECC

KW - error-correcting code

KW - OLSC

KW - on-chip interconnection

KW - orthogonal Latin square

KW - resilience and low power design

UR - https://www.scopus.com/pages/publications/79953654204

U2 - 10.1109/MDT.2011.35

DO - 10.1109/MDT.2011.35

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IS - 2

M1 - 5739839

ER -

Low-power, resilient interconnection with orthogonal latin squares

Abstract

UN SDGs

Keywords

Access to Document

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