TY - JOUR
T1 - Memristor binarized neural networks
AU - Pham, Khoa Van
AU - Nguyen, Tien Van
AU - Tran, Son Bao
AU - Nam, Hyun Kyung
AU - Lee, Mi Jung
AU - Choi, Byung Joon
AU - Truong, Son Ngoc
AU - Min, Kyeong Sik
N1 - Publisher Copyright:
© 2018, Institute of Electronics Engineers of Korea. All rights reserved.
PY - 2018/10
Y1 - 2018/10
N2 - Binarized Neural Networks (BNNs) use only binary synapses of +1 and-1, not allowing any intermediate weights between-1 and +1. Though the recognition rate of BNNs is lower than the conventional Deep Neural Networks (DNNs), BNNs have attracted many interests nowadays, because BNNs do not need the complicated multiplication such as DNNs. Binary memristor crossbars can be very suitable to realize BNN hardware. This is because, in memristor BNNs, simple binary operation can be performed in bitwise manner for all the columns in memristor crossbars, simultaneously. In this paper, single-column and double-column memristor BNNs are presented, respectively. In addition, ReLU and sigmoid activation function circuits are also proposed with CMOS circuits. The designed Memristor-CMOS hybrid circuits of BNNs have been tested for MNIST vectors. The memristor BNNs could recognize almost 90% MNIST digits when the memristance variation is as large as 25%. For variation tolerance, the memristor BNNs are compared with the multi-valued memristor neural networks such as 4-bit, 6-bit, etc, in this paper. As a result, it has been confirmed the memristor BNNs become more variation-tolerant than the multi-valued memristor NNs when the variation becomes larger than 22%. Comparing the single-column and double-column BNNs in this paper indicates that the single-column BNN can save power consumption and array area almost by half than the double-column. This is because the single-column has just half memristors than the double-column. And, we measured the single-column and double-column BNNs using the fabricated memristor array. In this measurement, both the double-column and single-column BNNs were observed to work well.
AB - Binarized Neural Networks (BNNs) use only binary synapses of +1 and-1, not allowing any intermediate weights between-1 and +1. Though the recognition rate of BNNs is lower than the conventional Deep Neural Networks (DNNs), BNNs have attracted many interests nowadays, because BNNs do not need the complicated multiplication such as DNNs. Binary memristor crossbars can be very suitable to realize BNN hardware. This is because, in memristor BNNs, simple binary operation can be performed in bitwise manner for all the columns in memristor crossbars, simultaneously. In this paper, single-column and double-column memristor BNNs are presented, respectively. In addition, ReLU and sigmoid activation function circuits are also proposed with CMOS circuits. The designed Memristor-CMOS hybrid circuits of BNNs have been tested for MNIST vectors. The memristor BNNs could recognize almost 90% MNIST digits when the memristance variation is as large as 25%. For variation tolerance, the memristor BNNs are compared with the multi-valued memristor neural networks such as 4-bit, 6-bit, etc, in this paper. As a result, it has been confirmed the memristor BNNs become more variation-tolerant than the multi-valued memristor NNs when the variation becomes larger than 22%. Comparing the single-column and double-column BNNs in this paper indicates that the single-column BNN can save power consumption and array area almost by half than the double-column. This is because the single-column has just half memristors than the double-column. And, we measured the single-column and double-column BNNs using the fabricated memristor array. In this measurement, both the double-column and single-column BNNs were observed to work well.
KW - Memristor binarized neural networks
KW - Memristor crossbars
KW - Memristor-cmos hybrid circuits
UR - https://www.scopus.com/pages/publications/85056334669
U2 - 10.5573/JSTS.2018.18.5.568
DO - 10.5573/JSTS.2018.18.5.568
M3 - Article
AN - SCOPUS:85056334669
SN - 1598-1657
VL - 18
SP - 568
EP - 577
JO - Journal of Semiconductor Technology and Science
JF - Journal of Semiconductor Technology and Science
IS - 5
ER -