Modeling of trapping induced threshold voltage shift dependency on a time-varying gate bias in thin-film transistors

The author has developed a discrete model for simulation to calculate the threshold voltage (V _T) shift caused by charge trapping and detrapping in a thin film transistor (TFT) under a time-varying bias. The model divides continuous states into discrete states and simplifies tunneling among the discrete states to keep track of their occupancies. The simulation is carried out for a TFT that has traps in the gate dielectric uniformly distributed perpendicular to the semiconductor/dielectric interface and the results account for the stretched-exponential time dependence of V _T shift.