Monolithic 3D Integration of Dual-Gated ALD Oxide-Channel Non-Volatile Capacitive Memory on 40nm Si CMOS for Digital Compute-in-Memory

We experimentally demonstrate monolithic 3D (M3D) integration of dual-gated (DG) non-volatile capacitive memory (nvCAP) featuring an ALD W-doped In₂O₃ (IWO) channel on a TSMC N40 CMOS foundry chip. Key technical advancements include: i) Novel dual-gate engineering of nvCAP, effectively addressing the weak erase and poor retention challenges with oxide-channel ferroelectrics; ii) First successful BEOL integration of DG nvCAP on a foundry CMOS chip, achieving a non-destructive capacitive on/off ratio of ~64.4 at V_read=0 V - a record among reported BEOL-compatible nvCAPs; iii) Non-destructive read endurance exceeding 10⁹ cycles at |V_read|=1 V, achieved in BEOL-integrated DG nvCAPs; iv) Introduction of the M3D non-destructive "capacitive"digital-compute-in-memory (Cap-DCIM) paradigm, achieving 146× higher figure-of-merit (TOPS/W×TOPS/mm²) compared to leading analog CIMs and 111× lower static power versus SRAM-based DCIMs - enabled by highly scalable digital logic and BEOL integration of DG nvCAPs. Finally, we experimentally validate the operational principle of M3D Cap-DCIM, by demonstrating BEOL capacitance-modulated FEOL Si transistor current amplification through monolithically integrated DG nvCAP on a foundry CMOS chip. These advancements offer a promising pathway to overcome the long-standing scalability and variability limitations of leading analog CIM approaches.