Abstract
A compact × 64 magnetic RAM (MRAM)-based analog computing-in-memory (ACIM) macro is presented, co-optimizing in-memory techniques to overcome the inherently small read margin of MRAM-based ACIM. Based on a single word-line and dual bit-lines weight configuration, two key features are developed. The first is in-memory calibration that utilizes the array itself to mitigate sense amplifier (SA) mismatches without additional circuitry, while the proposed counter-based scheme is designed to enable efficient built-in self-calibration with minimal digital overhead. The other technique is a reconfigurable in-memory reference ADC, which generates 2-bit outputs using only a single SA by leveraging programmable reference arrays with reconfigurable levels. The macro achieves high energy efficiency, area-normalized throughput, and inference accuracy on CIFAR-10: 121.9 1b-TOPS/W, 115.1 1b-TOPS/mm2, and 84.61% for the 1b input/weight/output case, and 27.3 1b-TOPS/W, 23.2 1b-TOPS/mm2, and 90.48% for the 2b input, 3b weight, and 6b output cases, respectively. By leveraging in-memory techniques to minimize peripheral overhead, this work demonstrates that practical and scalable multi-bit ACIM can be realized with high energy and area efficiency.
| Original language | English |
|---|---|
| Pages (from-to) | 59506-59513 |
| Number of pages | 8 |
| Journal | IEEE Access |
| Volume | 14 |
| DOIs | |
| State | Published - 2026 |
Keywords
- ADC
- MRAM
- computing-in-memory
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