Novel Stacked Floating Fin Structure Gate-All-Around Field-Effect Transistor for Design and Power Optimization

  • Munhyeon Kim
  • , Kitae Lee
  • , Sihyun Kim
  • , Soyoun Kim
  • , Sangwan Kim
  • , Byung Gook Park

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Due to high power density of stacked nanosheet gate-all-around field-effect transistor (GAAFET), device structure should be optimized. In this paper, an optimized nanosheet (NS) transistor based on inverter cell structure to reduce capacitance for low power operation is proposed and analyzed. The impact of the proposed structure on the device characteristic is analyzed through simulated power, performance and area (PPA) analysis. And capacitance variation induced by stacked NS GAAFET is also analyzed.

Original languageEnglish
Title of host publication2019 Electron Devices Technology and Manufacturing Conference, EDTM 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages136-138
Number of pages3
ISBN (Electronic)9781538665084
DOIs
StatePublished - Mar 2019
Event2019 Electron Devices Technology and Manufacturing Conference, EDTM 2019 - Singapore, Singapore
Duration: 12 Mar 201915 Mar 2019

Publication series

Name2019 Electron Devices Technology and Manufacturing Conference, EDTM 2019

Conference

Conference2019 Electron Devices Technology and Manufacturing Conference, EDTM 2019
Country/TerritorySingapore
CitySingapore
Period12/03/1915/03/19

Keywords

  • Gate-all-around FETs
  • PPA
  • Variation

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