On the FPGA Implementation of Binary Phase-ShiftKeying baseband Modem

In this paper, we implement a binary phase-shift keying (BPSK) modulation baseband communication MODEM using FPGA. We analyze and compare the theoretical bit error rate (BER), the computer simulated BER, and the BER obtained through the modem hardware implemented by FPGA in AWGN channel environments. A floating-point BER performance is determined using a MATLAB simulation. In order to obtain the performance of the MODEM hardware based on the fixed-point operation, we first predict the MODEM hardware output using a software package ‘Modelsim’ and then measure the actual bit error at the output of the FPGA hardware. Our experimental results show that the theoretical floating-point BER is 0.5dBsuperior to the
measured fixed-point BER of MODEM hardware when the internal register of the FPGA is restricted to 10 bits. It is also observed that the performance difference is reduced as the number of bits of the FPGA internal registers increases.