Optimal power reduction based on DVFS algorithm for video decoders

Seungho Jeong, Heejune Ahn

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

This paper proposes an optimal DVFS (Dynamic Voltage and Frequency Scaling) scheduling algorithm for decoders. Many DVFS techniques for video decoders have been proposed as a system level power-reduction technique. In this paper, based on the similarity in the system model with the 'Maximal Traffic Smoothing Algorithm [1],' an optimal scheduling algorithm and its schedulable conditions are presented. The simulation results show the optimal algorithm outperforms the previous heuristic algorithms by 7% on average. Furthermore, the performance gain saturates at about 10 frame size of the display buffers, i.e. the GOP level.

Original languageEnglish
Title of host publicationProceedings of the 2011 ACM Research in Applied Computation Symposium, RACS 2011
Pages107-109
Number of pages3
DOIs
StatePublished - 2011
Event2011 ACM Research in Applied Computation Symposium, RACS 2011 - Miami, FL, United States
Duration: 2 Nov 20115 Nov 2011

Publication series

NameProceedings of the 2011 ACM Research in Applied Computation Symposium, RACS 2011

Conference

Conference2011 ACM Research in Applied Computation Symposium, RACS 2011
Country/TerritoryUnited States
CityMiami, FL
Period2/11/115/11/11

Keywords

  • DVFS
  • embedded system
  • majorization theory
  • optimal theory
  • video decoder

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