Partial isolation type buried channel array transistor (Pi-bcat) for a sub-20 nm dram cell transistor

In this paper, we propose a new buried channel array transistor structure to solve the problem of current leakage occurring in the capacitors of dynamic random-access memory (DRAM) cells. This structure has a superior off current performance compared with three previous types of structures. In particular, the proposed buried channel array transistor has a 43% lower off current than the conventional asymmetric doping structure. Here, we show the range of the effective buried insulator parameter according to the depth of the buried gate, and we effectively show the range of improvement for the off current.