TY - JOUR
T1 - Positive feedback field effect transistor based on vertical NAND flash structure for in-memory computing
AU - Lee, Junhyeong
AU - Kwon, Min Woo
N1 - Publisher Copyright:
© 2024 The Japan Society of Applied Physics.
PY - 2024/2/29
Y1 - 2024/2/29
N2 - The distance between memory and central processing unit has led to a memory wall. To solve it, an in-memory technology that performs both memory and computation has been studied. To realize an ideal in-memory computing, we propose a positive feedback FET based on vertical NAND flash structure that can act as a memory and perform computation. The device can reconfigure the processing operations into AND or OR operations depending on the control gate bias. It performs memory by accumulating charge in the body, and logic operations can be performed by reading data stored in the charge trap layer. After this, it can also perform a writing operation. This component enables memory and read-compute-write operations, making it capable of implementing intrinsic in-memory computing. As a result, in this study, we designed and verified a structure that implements the core principles of in-memory computing.
AB - The distance between memory and central processing unit has led to a memory wall. To solve it, an in-memory technology that performs both memory and computation has been studied. To realize an ideal in-memory computing, we propose a positive feedback FET based on vertical NAND flash structure that can act as a memory and perform computation. The device can reconfigure the processing operations into AND or OR operations depending on the control gate bias. It performs memory by accumulating charge in the body, and logic operations can be performed by reading data stored in the charge trap layer. After this, it can also perform a writing operation. This component enables memory and read-compute-write operations, making it capable of implementing intrinsic in-memory computing. As a result, in this study, we designed and verified a structure that implements the core principles of in-memory computing.
KW - data processing
KW - feedback field effect transistor (FBFET)
KW - in-memory computing
KW - nand flash memory
KW - reconfigurable logic
KW - semiconductor memories
UR - https://www.scopus.com/pages/publications/85183181118
U2 - 10.35848/1347-4065/ad18a1
DO - 10.35848/1347-4065/ad18a1
M3 - Article
AN - SCOPUS:85183181118
SN - 0021-4922
VL - 63
JO - Japanese Journal of Applied Physics
JF - Japanese Journal of Applied Physics
IS - 2
M1 - 02SP56
ER -