TY - GEN
T1 - Power-aware design with various low-power algorithms for an H.264/AVC encoder
AU - Kim, Hyun
AU - Rhee, Chae Eun
AU - Kim, Jin Sung
AU - Kim, Sunwoong
AU - Lee, Hyuk Jae
PY - 2011
Y1 - 2011
N2 - H.264/AVC video compression standard provides high coding efficiency, but requires a considerable amount of complexity and power consumption. This paper presents advanced low-power algorithms for an H.264/AVC encoder and a power-aware design composed of low-power algorithms. Power reduction algorithms with frame memory compression and early skip mode decision are presented, and the search range for motion estimation is reduced for further power reduction. The proposed power-aware design controls the power consumption depending on the remaining energy by controlling the operation condition of the proposed low-power algorithms. In order to estimate the power reduction by the proposed algorithms, the power consumed by external memory as well as the bus between an H.264 encoder and an external DRAM is considered. Simulation results show that up to 49.9% of the power consumed by bus and external memory is reduced and that the power consumption from 0% to 41.56% is achieved with a reasonably small degradation of R-D performance.
AB - H.264/AVC video compression standard provides high coding efficiency, but requires a considerable amount of complexity and power consumption. This paper presents advanced low-power algorithms for an H.264/AVC encoder and a power-aware design composed of low-power algorithms. Power reduction algorithms with frame memory compression and early skip mode decision are presented, and the search range for motion estimation is reduced for further power reduction. The proposed power-aware design controls the power consumption depending on the remaining energy by controlling the operation condition of the proposed low-power algorithms. In order to estimate the power reduction by the proposed algorithms, the power consumed by external memory as well as the bus between an H.264 encoder and an external DRAM is considered. Simulation results show that up to 49.9% of the power consumed by bus and external memory is reduced and that the power consumption from 0% to 41.56% is achieved with a reasonably small degradation of R-D performance.
UR - https://www.scopus.com/pages/publications/79960873962
U2 - 10.1109/ISCAS.2011.5937629
DO - 10.1109/ISCAS.2011.5937629
M3 - Conference contribution
AN - SCOPUS:79960873962
SN - 9781424494736
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 571
EP - 574
BT - 2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011
T2 - 2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011
Y2 - 15 May 2011 through 18 May 2011
ER -