Reduced power consumption Current-mode ADC using SAR logic for AI application

Soyoun Park; Hyungmin Kim; Daniel Juhun Lee; Taemin Nho; Seongkweon Kim; Dongha Shim

doi:10.1109/ISOCC50952.2020.9332945

Reduced power consumption Current-mode ADC using SAR logic for AI application

Soyoun Park
, Hyungmin Kim
, Daniel Juhun Lee
, Taemin Nho
, Seongkweon Kim
, Dongha Shim

Seoul National University of Science and Technology (SNUST)

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

This paper introduces a new SAR logic that does not need to refer to the upper digital bits to overcome the limitation that the speed can be limited by the conversion time of the comparator by using conventional SAR logic. This proposed logic can be applied to a current-mode flash type ADC and it can be realized with a system consisting of current comparators, encoders and an input generator made up of current rectifiers. The proposed circuit has been implemented using 0.18-um CMOS technology. This circuit operates at a supply voltage of 3.3-V and its input current range is 0-100 μA. The active layout area of the 6-bit current-mode ADC is 341-μm×158 μm, The power consumption is estimated to be 2.4-mW when the input frequency is 100 kHz.

Original language	English
Title of host publication	Proceedings - International SoC Design Conference, ISOCC 2020
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	256-257
Number of pages	2
ISBN (Electronic)	9781728183312
DOIs	https://doi.org/10.1109/ISOCC50952.2020.9332945
State	Published - 21 Oct 2020
Event	17th International System-on-Chip Design Conference, ISOCC 2020 - Yeosu, Korea, Republic of Duration: 21 Oct 2020 → 24 Oct 2020

Publication series

Name	Proceedings - International SoC Design Conference, ISOCC 2020

Conference

Conference	17th International System-on-Chip Design Conference, ISOCC 2020
Country/Territory	Korea, Republic of
City	Yeosu
Period	21/10/20 → 24/10/20

Keywords

ADC
current-mode
SAR logic

Access to Document

10.1109/ISOCC50952.2020.9332945

Cite this

Park, S., Kim, H., Lee, D. J., Nho, T., Kim, S., & Shim, D. (2020). Reduced power consumption Current-mode ADC using SAR logic for AI application. In Proceedings - International SoC Design Conference, ISOCC 2020 (pp. 256-257). Article 9332945 (Proceedings - International SoC Design Conference, ISOCC 2020). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC50952.2020.9332945

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title = "Reduced power consumption Current-mode ADC using SAR logic for AI application",

abstract = "This paper introduces a new SAR logic that does not need to refer to the upper digital bits to overcome the limitation that the speed can be limited by the conversion time of the comparator by using conventional SAR logic. This proposed logic can be applied to a current-mode flash type ADC and it can be realized with a system consisting of current comparators, encoders and an input generator made up of current rectifiers. The proposed circuit has been implemented using 0.18-um CMOS technology. This circuit operates at a supply voltage of 3.3-V and its input current range is 0-100 μA. The active layout area of the 6-bit current-mode ADC is 341-μm×158 μm, The power consumption is estimated to be 2.4-mW when the input frequency is 100 kHz.",

keywords = "ADC, current-mode, SAR logic",

author = "Soyoun Park and Hyungmin Kim and Lee, \{Daniel Juhun\} and Taemin Nho and Seongkweon Kim and Dongha Shim",

note = "Publisher Copyright: {\textcopyright} 2020 IEEE.; 17th International System-on-Chip Design Conference, ISOCC 2020 ; Conference date: 21-10-2020 Through 24-10-2020",

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Park, S, Kim, H, Lee, DJ, Nho, T, Kim, S & Shim, D 2020, Reduced power consumption Current-mode ADC using SAR logic for AI application. in Proceedings - International SoC Design Conference, ISOCC 2020., 9332945, Proceedings - International SoC Design Conference, ISOCC 2020, Institute of Electrical and Electronics Engineers Inc., pp. 256-257, 17th International System-on-Chip Design Conference, ISOCC 2020, Yeosu, Korea, Republic of, 21/10/20. https://doi.org/10.1109/ISOCC50952.2020.9332945

Reduced power consumption Current-mode ADC using SAR logic for AI application. / Park, Soyoun; Kim, Hyungmin; Lee, Daniel Juhun et al.
Proceedings - International SoC Design Conference, ISOCC 2020. Institute of Electrical and Electronics Engineers Inc., 2020. p. 256-257 9332945 (Proceedings - International SoC Design Conference, ISOCC 2020).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Reduced power consumption Current-mode ADC using SAR logic for AI application

AU - Park, Soyoun

AU - Kim, Hyungmin

AU - Lee, Daniel Juhun

AU - Nho, Taemin

AU - Kim, Seongkweon

AU - Shim, Dongha

PY - 2020/10/21

Y1 - 2020/10/21

N2 - This paper introduces a new SAR logic that does not need to refer to the upper digital bits to overcome the limitation that the speed can be limited by the conversion time of the comparator by using conventional SAR logic. This proposed logic can be applied to a current-mode flash type ADC and it can be realized with a system consisting of current comparators, encoders and an input generator made up of current rectifiers. The proposed circuit has been implemented using 0.18-um CMOS technology. This circuit operates at a supply voltage of 3.3-V and its input current range is 0-100 μA. The active layout area of the 6-bit current-mode ADC is 341-μm×158 μm, The power consumption is estimated to be 2.4-mW when the input frequency is 100 kHz.

AB - This paper introduces a new SAR logic that does not need to refer to the upper digital bits to overcome the limitation that the speed can be limited by the conversion time of the comparator by using conventional SAR logic. This proposed logic can be applied to a current-mode flash type ADC and it can be realized with a system consisting of current comparators, encoders and an input generator made up of current rectifiers. The proposed circuit has been implemented using 0.18-um CMOS technology. This circuit operates at a supply voltage of 3.3-V and its input current range is 0-100 μA. The active layout area of the 6-bit current-mode ADC is 341-μm×158 μm, The power consumption is estimated to be 2.4-mW when the input frequency is 100 kHz.

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T3 - Proceedings - International SoC Design Conference, ISOCC 2020

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BT - Proceedings - International SoC Design Conference, ISOCC 2020

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Park S, Kim H, Lee DJ, Nho T, Kim S , Shim D. Reduced power consumption Current-mode ADC using SAR logic for AI application. In Proceedings - International SoC Design Conference, ISOCC 2020. Institute of Electrical and Electronics Engineers Inc. 2020. p. 256-257. 9332945. (Proceedings - International SoC Design Conference, ISOCC 2020). doi: 10.1109/ISOCC50952.2020.9332945

Reduced power consumption Current-mode ADC using SAR logic for AI application

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