Reduction of the Hysteresis Voltage in Atomic-Layer-Deposited p-Type SnO Thin-Film Transistors by Adopting an Al₂O₃ Interfacial Layer

The origin of hysteresis in the drain–source current (I_DS)–gate-source voltage (V_GS) characteristics of atomic-layer-deposited (ALD) p-type SnO thin-film transistors (TFTs) is examined by adding ALD Al₂O₃ interfacial layers (IL) between the SnO channel layer and the SiO₂ gate insulator (GI) layer. SnO TFTs with SiO₂ GI exhibit a large hysteresis voltage (V_hy) due to the trap state density near the interface between the SnO active layer and the SiO₂ GI (known as the border trap). Both experimental results and theoretical calculations show that the origin of border traps is the Sn_Si⁺⁰ gap states in SiO₂, which is induced by the Sn diffusion into the SiO₂ layer. The use of Al₂O₃ films as ILs suppresses this diffusion. The effectiveness, however, is dependent on the thickness, crystallinity, and density of the Al₂O₃ films. The V_hy of the SnO TFTs can be decreased when the thickness and density of the ILs is increased if the amorphous structure of the Al₂O₃ IL is maintained after the rapid thermal annealing process. p-Type ALD SnO TFTs with optimum ILs exhibit a high on-off ratio of I_DS (1.2 × 10⁵), high field-effect mobility (1.6 cm² V⁻¹ s⁻¹), and a small V_hy (0.2 V).