TY - JOUR
T1 - Regression Model-Based AMS Circuit Optimization Technique Utilizing Parameterized Operating Condition
AU - Nam, Jae Won
AU - Cho, Young Kyun
AU - Lee, Youn Kyu
N1 - Publisher Copyright:
© 2022 by the authors. Licensee MDPI, Basel, Switzerland.
PY - 2022/2/1
Y1 - 2022/2/1
N2 - An analog and mixed-signal (AMS) circuit that draws on machine learning while using a regression model differs in terms of the design compared to more sophisticated circuit designs. Technology structures that are more advanced than conventional CMOS processes, specifically the fin field-effect transistor (FinFET) and silicon-on-insulator (SOI), have been proposed to provide the higher computation performance required to meet various design specifications. As a result, the latest research on AMS design optimization has enabled enormous resource savings in AMS design procedures but remains limited with regard to reflecting the intended operating conditions in the design parameters. Hereby, we propose what is termed a supervised learning artificial neural network (ANN) as a means by which to define an AMS regression model. This approach allows for rapid searches of complex design dimensions, including variations in performance metrics caused by process–voltage–temperature (PVT) changes. The method also reduces the considerable computation expense compared to that of simulation-program-with-integrated-circuit-emphasis (SPICE) simulations. Hence, the proposed AMS circuit design flow generates highly promising output to meet target requirements while showing an excellent ability to match the design target performance. To verify the potential and promise of our design flow, a successive approximation register analog-to-digital converter (SAR ADC) is designed with a 14 nm process design kit. In order to show the maximum single ADC performance (6-bit∼8-bit resolution and few GS/s conversion speed), we have set three different ADC performance targets. Under all SS/TT/FF corners, ±6.25% supply voltage variation, and temperature variation from −40◦ C to 80◦ C, the designed SAR ADC using our proposed AMS circuit optimization flow yields remarkable figure-of-merit energy efficiency (approximately 15 fJ/conversion step).
AB - An analog and mixed-signal (AMS) circuit that draws on machine learning while using a regression model differs in terms of the design compared to more sophisticated circuit designs. Technology structures that are more advanced than conventional CMOS processes, specifically the fin field-effect transistor (FinFET) and silicon-on-insulator (SOI), have been proposed to provide the higher computation performance required to meet various design specifications. As a result, the latest research on AMS design optimization has enabled enormous resource savings in AMS design procedures but remains limited with regard to reflecting the intended operating conditions in the design parameters. Hereby, we propose what is termed a supervised learning artificial neural network (ANN) as a means by which to define an AMS regression model. This approach allows for rapid searches of complex design dimensions, including variations in performance metrics caused by process–voltage–temperature (PVT) changes. The method also reduces the considerable computation expense compared to that of simulation-program-with-integrated-circuit-emphasis (SPICE) simulations. Hence, the proposed AMS circuit design flow generates highly promising output to meet target requirements while showing an excellent ability to match the design target performance. To verify the potential and promise of our design flow, a successive approximation register analog-to-digital converter (SAR ADC) is designed with a 14 nm process design kit. In order to show the maximum single ADC performance (6-bit∼8-bit resolution and few GS/s conversion speed), we have set three different ADC performance targets. Under all SS/TT/FF corners, ±6.25% supply voltage variation, and temperature variation from −40◦ C to 80◦ C, the designed SAR ADC using our proposed AMS circuit optimization flow yields remarkable figure-of-merit energy efficiency (approximately 15 fJ/conversion step).
KW - AMS
KW - Artificial neural network
KW - FinFET
KW - Machine learning
KW - PVT
KW - SAR ADC
KW - SOI process
UR - http://www.scopus.com/inward/record.url?scp=85123518962&partnerID=8YFLogxK
U2 - 10.3390/electronics11030408
DO - 10.3390/electronics11030408
M3 - Article
AN - SCOPUS:85123518962
SN - 2079-9292
VL - 11
JO - Electronics (Switzerland)
JF - Electronics (Switzerland)
IS - 3
M1 - 408
ER -