RF2P: A Lightweight RISC Processor Optimized for Rapid Migration from IEEE-754 to Posit

Hyun Woo Oh, Seongmo An, Won Sik Jeong, Seung Eun Lee

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

This paper presents a lightweight processor and evaluation platform for migrating from IEEE-754 to posit arithmetic, with an optimized posit arithmetic unit (PAU) supporting existing floating-point instructions. The PAU features a reconfigurable divider architecture for diverse operating conditions and lightweight square root logic. The platform includes a posit-optimized compiler, divider generator, JTAG environment builder, and programmable logic controller. The experimental results demonstrate the successful execution of legacy IEEE-754 code with a small additional workload and up to 60.09 times the performance improvement through hardware acceleration. Additionally, the PAU and divider consume 11.00% and 57.87% fewer LUTs, respectively, compared to the best prior works.

Original languageEnglish
Title of host publication2023 IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2023
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9798350311754
DOIs
StatePublished - 2023
Event2023 IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2023 - Vienna, Austria
Duration: 7 Aug 20238 Aug 2023

Publication series

NameProceedings of the International Symposium on Low Power Electronics and Design
Volume2023-August
ISSN (Print)1533-4678

Conference

Conference2023 IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2023
Country/TerritoryAustria
CityVienna
Period7/08/238/08/23

Keywords

  • hardware acceleration
  • lightweight embedded systems
  • processor core
  • real number arithmetic
  • reduced instruction set computer

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