Self-biased anti-parallel diode pair in 130-nm CMOS

This Letter presents a self-biased anti-parallel diode pair (APDP) in a 130-nm standard digital CMOS process. The proposed device employs complementary polysilicon-gate-separated Schottky barrier diodes (SBDs). A parallel RC network in series with the n-well of n-type SBD connected in shunt is used to build-up the self-bias voltage that depends on the input power level. The device exhibits less roll-off in output harmonic power generation at a high input power level due to the automatic adjustment of the I-V curve. The measured cutoff frequency of the device reaches ∼530 GHz at zero-bias. Harmonic power measurements indicate that use of the self-biasing reduces saturation at high input power levels. The self-biased complementary- APDP (C-APDP) generates up to 5.7 dB higher third harmonic power than the cathode-tied C-APDP.