Sharing computation resources for large-scale recognition system-on-chip (SoC)

In this paper, we investigate image and speech recognition system flows and propose a data-path for both of recognition engines, reducing the hardware cost and power consumption of the recognition System-on-Chip (SoC). Implementation results demonstrate 6.5% of area and 25.5% of power reductions in data-path, compared to the dedicated data-path designs using 90nm CMOS technology. The proposed architecture provides sharing of the integrated SRAM and the control logic in the recognition engines, reducing the area cost and power consumption.