SiGe-Surrounded Bitline Structure for Enhancing 3D NAND Flash Erase Speed

Three-dimensional NAND Flash has adopted the cell-over-peripheral (COP) structure to increase storage density. Unlike the conventional structure, the COP structure cannot directly increase the channel potential via substrate bias during the erase operation. Therefore, the gate-induced drain leakage (GIDL) erase method, which utilizes band-to-band tunneling (BTBT) to raise the channel potential, is employed. However, compared to bulk erase, the BTBT-based erase method requires a longer time to generate holes in the channel, leading to erase speed degradation. To address this issue, we propose a structure which enhances the erase speed by surrounding the bitline (BL) PAD with SiGe. In the case of a SiGe thickness (t_SiGe) of 13 nm, the lower bandgap of SiGe increases the BTBT generation rate, boosting the channel potential rise at the end of the erase voltage ramp-up by 861% compared to the Si-only structure, while limiting the reduction in read on-current to within 4%. We modeled the voltage and electric field across the SiGe layer, as well as BTBT generation rate and GIDL current in the SiGe layer, by varying t_SiGe, Ge composition ratio (SiGe_X), and the voltage difference between V_BL and V_{GIDL_TR}.