TY - GEN
T1 - SRU-Q
T2 - 6th IEEE International Conference on AI Circuits and Systems, AICAS 2024
AU - Jeong, Sangbeom
AU - Choi, Dahun
AU - Kim, Hyun
N1 - Publisher Copyright:
© 2024 IEEE.
PY - 2024
Y1 - 2024
N2 - Quantization in convolutional neural networks (CNNs) involves using a low precision to decrease convolution operation costs, resulting in reduced power consumption and faster network performance. Notably, gradient quantization plays a crucial role in CNN training accelerators, as backpropagation typically incurs higher computational costs for calculating weight gradients than forward propagation does. Stochastic rounding (SR), which employs random number generation, is recognized as an effective method for stabilizing backpropagation quantization. However, the process of generating random numbers in hardware has significant drawbacks - notably high computational costs and substantial difficulties in implementation. This paper introduces a technique for efficient SR using a hardware-optimized random number generator, termed linear feedback shift register-bitwise-stochastic rounding unit (LBSRU). The LBSRU efficiently conducts SR with a small amount of random number generation and adapts to various network types by altering the random number generation approach for different batch sizes. Specifically, we designed and synthesized our method on the FPGA platform to create a prototype. A comparison with previous studies revealed that our method requires significantly fewer resources: 98.19% fewer lookup tables (LUTs) and 98.38% fewer flip-flops (FFs).
AB - Quantization in convolutional neural networks (CNNs) involves using a low precision to decrease convolution operation costs, resulting in reduced power consumption and faster network performance. Notably, gradient quantization plays a crucial role in CNN training accelerators, as backpropagation typically incurs higher computational costs for calculating weight gradients than forward propagation does. Stochastic rounding (SR), which employs random number generation, is recognized as an effective method for stabilizing backpropagation quantization. However, the process of generating random numbers in hardware has significant drawbacks - notably high computational costs and substantial difficulties in implementation. This paper introduces a technique for efficient SR using a hardware-optimized random number generator, termed linear feedback shift register-bitwise-stochastic rounding unit (LBSRU). The LBSRU efficiently conducts SR with a small amount of random number generation and adapts to various network types by altering the random number generation approach for different batch sizes. Specifically, we designed and synthesized our method on the FPGA platform to create a prototype. A comparison with previous studies revealed that our method requires significantly fewer resources: 98.19% fewer lookup tables (LUTs) and 98.38% fewer flip-flops (FFs).
KW - convolutional neural networks
KW - FPGA
KW - gradient quantization
KW - random number generator
KW - stochastic rounding
UR - http://www.scopus.com/inward/record.url?scp=85199885114&partnerID=8YFLogxK
U2 - 10.1109/AICAS59952.2024.10595985
DO - 10.1109/AICAS59952.2024.10595985
M3 - Conference contribution
AN - SCOPUS:85199885114
T3 - 2024 IEEE 6th International Conference on AI Circuits and Systems, AICAS 2024 - Proceedings
SP - 457
EP - 461
BT - 2024 IEEE 6th International Conference on AI Circuits and Systems, AICAS 2024 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 22 April 2024 through 25 April 2024
ER -