Stacked chip-to-chip interconnections using wafer bonding technology with dielectric bonding glues

J. Q. Lü; Y. Kwon; R. P. Kraft; R. J. Gutmann; J. F. McDonald; T. S. Gale

doi:10.1109/IITC.2001.930066

Stacked chip-to-chip interconnections using wafer bonding technology with dielectric bonding glues

J. Q. Lü, Y. Kwon, R. P. Kraft, R. J. Gutmann, J. F. McDonald, T. S. Gale

Dept. of Chemical and Biomolecular Engineering

Rensselaer Polytechnic Institute

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

45 Scopus citations

Abstract

Three-dimensional (3D) interconnects offer the potential of reducing fabrication and performance limitations of future generations of planar ICs. This paper describes a specific approach, incorporating wafer alignment and wafer bonding of two 200-mm silicon wafers, along with subsequent processing steps. Our approach using dielectrics as the bonding glue layer provides a monolithic 3D interconnect process, which is fully compatible with back-end-of-the-line processing. This 3D technology enables heterogeneous systems, such as future electronic and photonic systems using a mix-and-match hard IP core design approach, and provides a high-density pin-out alternative to stacked chip-scale packages today.

Original language	English
Title of host publication	Proceedings of the IEEE 2001 International Interconnect Technology Conference, IITC 2001
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	219-221
Number of pages	3
ISBN (Electronic)	0780366786, 9780780366787
DOIs	https://doi.org/10.1109/IITC.2001.930066
State	Published - 2001
Event	IEEE International Interconnect Technology Conference, IITC 2001 - Burlingame, United States Duration: 4 Jun 2001 → 6 Jun 2001

Publication series

Name	Proceedings of the IEEE 2001 International Interconnect Technology Conference, IITC 2001

Conference

Conference	IEEE International Interconnect Technology Conference, IITC 2001
Country/Territory	United States
City	Burlingame
Period	4/06/01 → 6/06/01

Access to Document

10.1109/IITC.2001.930066

Cite this

Lü, J. Q., Kwon, Y., Kraft, R. P., Gutmann, R. J., McDonald, J. F., & Gale, T. S. (2001). Stacked chip-to-chip interconnections using wafer bonding technology with dielectric bonding glues. In Proceedings of the IEEE 2001 International Interconnect Technology Conference, IITC 2001 (pp. 219-221). Article 930066 (Proceedings of the IEEE 2001 International Interconnect Technology Conference, IITC 2001). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IITC.2001.930066

Lü, J. Q. ; Kwon, Y. ; Kraft, R. P. et al. / Stacked chip-to-chip interconnections using wafer bonding technology with dielectric bonding glues. Proceedings of the IEEE 2001 International Interconnect Technology Conference, IITC 2001. Institute of Electrical and Electronics Engineers Inc., 2001. pp. 219-221 (Proceedings of the IEEE 2001 International Interconnect Technology Conference, IITC 2001).

@inproceedings{08eeb7afd6264a26a3f441bd92a8f381,

title = "Stacked chip-to-chip interconnections using wafer bonding technology with dielectric bonding glues",

abstract = "Three-dimensional (3D) interconnects offer the potential of reducing fabrication and performance limitations of future generations of planar ICs. This paper describes a specific approach, incorporating wafer alignment and wafer bonding of two 200-mm silicon wafers, along with subsequent processing steps. Our approach using dielectrics as the bonding glue layer provides a monolithic 3D interconnect process, which is fully compatible with back-end-of-the-line processing. This 3D technology enables heterogeneous systems, such as future electronic and photonic systems using a mix-and-match hard IP core design approach, and provides a high-density pin-out alternative to stacked chip-scale packages today.",

author = "L{\"u}, \{J. Q.\} and Y. Kwon and Kraft, \{R. P.\} and Gutmann, \{R. J.\} and McDonald, \{J. F.\} and Gale, \{T. S.\}",

note = "Publisher Copyright: {\textcopyright} 2000 IEEE.; IEEE International Interconnect Technology Conference, IITC 2001 ; Conference date: 04-06-2001 Through 06-06-2001",

year = "2001",

doi = "10.1109/IITC.2001.930066",

language = "English",

series = "Proceedings of the IEEE 2001 International Interconnect Technology Conference, IITC 2001",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "219--221",

booktitle = "Proceedings of the IEEE 2001 International Interconnect Technology Conference, IITC 2001",

}

Lü, JQ, Kwon, Y, Kraft, RP, Gutmann, RJ, McDonald, JF & Gale, TS 2001, Stacked chip-to-chip interconnections using wafer bonding technology with dielectric bonding glues. in Proceedings of the IEEE 2001 International Interconnect Technology Conference, IITC 2001., 930066, Proceedings of the IEEE 2001 International Interconnect Technology Conference, IITC 2001, Institute of Electrical and Electronics Engineers Inc., pp. 219-221, IEEE International Interconnect Technology Conference, IITC 2001, Burlingame, United States, 4/06/01. https://doi.org/10.1109/IITC.2001.930066

Stacked chip-to-chip interconnections using wafer bonding technology with dielectric bonding glues. / Lü, J. Q.; Kwon, Y.; Kraft, R. P. et al.
Proceedings of the IEEE 2001 International Interconnect Technology Conference, IITC 2001. Institute of Electrical and Electronics Engineers Inc., 2001. p. 219-221 930066 (Proceedings of the IEEE 2001 International Interconnect Technology Conference, IITC 2001).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Stacked chip-to-chip interconnections using wafer bonding technology with dielectric bonding glues

AU - Lü, J. Q.

AU - Kwon, Y.

AU - Kraft, R. P.

AU - Gutmann, R. J.

AU - McDonald, J. F.

AU - Gale, T. S.

PY - 2001

Y1 - 2001

N2 - Three-dimensional (3D) interconnects offer the potential of reducing fabrication and performance limitations of future generations of planar ICs. This paper describes a specific approach, incorporating wafer alignment and wafer bonding of two 200-mm silicon wafers, along with subsequent processing steps. Our approach using dielectrics as the bonding glue layer provides a monolithic 3D interconnect process, which is fully compatible with back-end-of-the-line processing. This 3D technology enables heterogeneous systems, such as future electronic and photonic systems using a mix-and-match hard IP core design approach, and provides a high-density pin-out alternative to stacked chip-scale packages today.

AB - Three-dimensional (3D) interconnects offer the potential of reducing fabrication and performance limitations of future generations of planar ICs. This paper describes a specific approach, incorporating wafer alignment and wafer bonding of two 200-mm silicon wafers, along with subsequent processing steps. Our approach using dielectrics as the bonding glue layer provides a monolithic 3D interconnect process, which is fully compatible with back-end-of-the-line processing. This 3D technology enables heterogeneous systems, such as future electronic and photonic systems using a mix-and-match hard IP core design approach, and provides a high-density pin-out alternative to stacked chip-scale packages today.

UR - https://www.scopus.com/pages/publications/85001133965

U2 - 10.1109/IITC.2001.930066

DO - 10.1109/IITC.2001.930066

M3 - Conference contribution

AN - SCOPUS:85001133965

T3 - Proceedings of the IEEE 2001 International Interconnect Technology Conference, IITC 2001

SP - 219

EP - 221

BT - Proceedings of the IEEE 2001 International Interconnect Technology Conference, IITC 2001

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - IEEE International Interconnect Technology Conference, IITC 2001

Y2 - 4 June 2001 through 6 June 2001

ER -

Lü JQ, Kwon Y, Kraft RP, Gutmann RJ, McDonald JF, Gale TS. Stacked chip-to-chip interconnections using wafer bonding technology with dielectric bonding glues. In Proceedings of the IEEE 2001 International Interconnect Technology Conference, IITC 2001. Institute of Electrical and Electronics Engineers Inc. 2001. p. 219-221. 930066. (Proceedings of the IEEE 2001 International Interconnect Technology Conference, IITC 2001). doi: 10.1109/IITC.2001.930066

Stacked chip-to-chip interconnections using wafer bonding technology with dielectric bonding glues

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