Stress analysis of the low-k layer in a flip-chip package with an oblong copper pillar bump

The recent requirements for finer pitch and miniaturization of the package have drawn attention to flip chip technology with copper (Cu) pillar bump. The Cu bump, however, has a higher modulus compared to the solder bump and introduces high mechanical stress to a low-k layer in the chip. In this study, we investigated the low-k layer stress induced after reflow process. In particular, the effects of new technologies such as an oblong Cu bump and embedded trace substrate (ETS) on low-k layer stress were analyzed and compared with the conventional round Cu bump and substrate. For precise prediction of solder joint shape, Surface Evolver program was used. The effects of the Cu bump height and solder resist opening (SRO) diameter on the low-k layer stress were investigated. The oblong bump showed a low-k layer stress of 10% lower than the round bump, and ETS showed a low-k layer stress of 23% lower than the conventional substrate. Therefore, the employment of the oblong bump and ETS is very effective in reducing the low-k stress. In general, increasing the Cu bump height and decreasing the SRO diameter will reduce the low-k layer stress.