Study of thermo-mechanical reliability of TSV for 8-layer stacked multi chip package

Through silicon via (TSV) technology is becoming a hot topic for three dimensional integration in IC packaging industry. However, TSV technology raises several reliability concerns particularly caused by thermally induced stress. In this study, the thermo-mechanical reliability of copper TSV technology for the multi chip packaging (MCP) was investigated using finite element method. For the multi chip package design, the 8-layer stacked chip packaging with TSV structure has been constructed as our test vehicle. Fig.1 schematically shows the 8-layer MCP structure using the typical TSV interconnection technology. The silicon chips or dies are stacked and bonded using a SnAg solder, and a filling material is used to fill the gap between the silicon dies so as to protect the solder joints. The silicon dies are bonded to the silicon substrate. The typical thickness of silicon die is 50 μm, the gap between the silicon dies is 20 μm, and the thickness of SnAg solder joint is 4 μm respectively. The numerical analysis of stress/strain distribution and thermal fatigue life prediction were performed in order to study the impact of several design parameters such as via diameter, via pitch, die thickness, filling materials. FEM simulation with ANSYS, a commercial finite element analysis software, was used to investigate the thermal stress in 3D TSV structure caused by CTE mismatch of different packaging materials. The MCP structure is subjected to a thermal ramp from 125 °C to -40 °C. The stress-free temperature is assumed to be 125 °C. This paper focuses on the stress concentration around via hole, and whole package model needs a lot of elements and nodes. Therefore, the submodel(Fig. 2) with much finer meshes is employed to make accurate solutions for stress distribution around via and interface between different materials. 3D brick elements with 8-nodes are used for mesh, and the number of total elements is 15300. Copper is modeled as the kinematic hardening material to introduce the plastic effect due to high stress concentration. At each pitch, the calculated maximum von Mises stress in TSV structure increases as the via size decreases as shown in Fig.3. This trend makes sense because the cross section of the Cu decreases while the amount of stack it must constrain increases. On the while, in the case of different via size, the calculated von Mises stress increases with increasing pitch as shown in Fig.4. As the via size decreases up to 5 μm, the von Mises stress in Cu via becomes more than 300 MPa which either exceed or are close to the yield stress of copper. As the thickness of the silicon die increases, the change of stress is very slight. It was known that the employment of underfill or filling material is effective in reducing the thermal stresses and improving the reliability of stacked package. However, the optimal material properties of filling material are not fully understood yet. Therefore, thermal stress analysis was conducted to investigate the effects of various filling materials which have different Young's modulus and CTEs. Since filling materials are very diverse and their material properties are mainly dependent on complicated fabrication technique, we used typical filling materials which were used in several studies for numerical simulation. Fig.5 shows the results of von Mises stress used for different filling materials, which are ABF(Ajinomoto built-up film), Underfill, Epoxy, BCB(Benzocyclobutene), NUF(No Flow Underfill), respectively, and their material properties are shown in Table 1. The von Mises stress becomes the largest for ABF material, then larger for the BCB material, and the smallest for the NUF. Comparing the material propertis, CTE is the largest for the ABF, then larger for the BCB. The epoxy material which has the largest Young's modulus shows relatively lower stress. Therefore it is thought that CTE of filling material is most influential factor in Cu via stress. The DOE (design of experiment) analysis was also performed to find the optimal design conditions. Fig.6 shows the main effect plot of the results of DOE analysis. The most influential factors for the stress reduction are TSV diameter and the coefficient of thermal expansion of filling material. The larger via diameter and lower CTE of filling material showed the smaller stress distribution. Reliability of MCP structure used in this study was also confirmed by the numerical prediction of thermal fatigue life caused by thermal cycles with the distribution of plastic strain. The plastic strain was applied to Coffin-Manson model which is equation of fatigue life expectation, and then theoretical fatigue life was predicted. At first, the difference of plastic strain of the case with filling material and without filling material as increasing the size of via was compared. When there is no filling material, the plastic strain is 7∼8 times larger than the case of presence of filling material as shown in Fig.7. If there is no filling material, the plastic strain is occurred mainly at solders due to the larger CTE of SnAg solder than that of copper. The expected fatigue life shown in Fig.8 indicates that the presence of filling material is essential to maintain the longer life and improve durability of TSV structure. The plastic strain in the case of presence of filling material generally increases as the via size increases. Therefore, expected thermal fatigue life will increase as the via size decreases. The package materials around Cu via and pad could effectively protect copper from deforming as the via size decreases. However, the the smaller via shows the higher von Mises stress. It means that smaller via is not always safer even though it has longer life. In particular, the maximum plastic strain increases substantially for the case of the 100μm-pitch, 20μm-via size due to the complicated effects of the package around via and pad. Therefore carefull design consideration of via size and pitch are required for reliability improvement. The bonding pad design is also important for TSV durability. The smaller bonding pad showed less stress and higher thermal fatigue life. The characteristics of warpage for 8-layer multi chip package were also investigated.