Sub-30 nm Silicon Nanopatterning: Toward Reduced Reflectance and Enhanced Sensitivity in CMOS Image Sensors

This work investigated how subwavelength silicon patterning and dielectric passivation influence the optical and electrical performance of advanced CMOS image sensors (CIS). Hole arrays with sidewall angles of 73°, 79°, and 86° were fabricated using industrial plasma-etch processes, with and without aluminum-oxide/hafnium-oxide passivation and antireflective (AR) coatings. Reflectance measurements from 360-1000nm showed that etch geometry and dielectric filling substantially reduced Fresnel reflection, with the 79° profile achieving the lowest broadband reflectance and film-filled structures providing additional suppression in the blue-green region. Device-level evaluations on 0.64 μm-pixel CIS sensors demonstrated RGB sensitivity improvements of 0.7-3.3% under low illumination (23 lux, 30 ms), with no increase in crosstalk. These trends correlated closely with wafer-level reflectance, confirming reflectance as a reliable early predictor of device performance. Although certain etch conditions increased dark current due to plasma-induced damage, the aluminumoxide /hafnium-oxide passivation stack effectively mitigated interface traps, enabling stable electrical behavior for optimized profiles. Overall, the results demonstrated that co-optimizing etch geometry, dielectric materials, and process conditions enhances both optical efficiency and electrical robustness, providing a manufacturable path toward higher-sensitivity CIS devices in submicron-pixel technology.