Surface-controlled ultrathin (2 nm) Poly-Si channel junctionless FET towards 3D NAND flash memory applications

Jong Kyung Park; Seung Yoon Kim; Ki Hong Lee; Seung Ho Pyi; Seok Hee Lee; Byung Jin Cho

doi:10.1109/VLSIT.2014.6894385

Surface-controlled ultrathin (2 nm) Poly-Si channel junctionless FET towards 3D NAND flash memory applications

Jong Kyung Park, Seung Yoon Kim, Ki Hong Lee, Seung Ho Pyi, Seok Hee Lee, Byung Jin Cho

Dept. of Semiconductor Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

17 Scopus citations

Abstract

An ultrathin junctionless (JL) charge trap flash (CTF) thin-film transistor (TFT) with a sub-2 nm thick poly-Si channel is demonstrated for 3D stacked flash memory. It provides the excellent memory performance of faster program/erase (P/E) speed, larger memory window (>12 V), and better endurance (>10⁴ cycles) than inversion-mode (IM) devices; this device also has excellent 10-year data retention at 150 °C, as well as improved on/off current ratio (>10⁸) and subthreshold swing (SS). The transfer characteristics and the memory performance as a function of the poly-Si channel thickness (T_Ch) are also systematically investigated.

Original language	English
Title of host publication	Digest of Technical Papers - Symposium on VLSI Technology
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781479933310
DOIs	https://doi.org/10.1109/VLSIT.2014.6894385
State	Published - 8 Sep 2014
Event	34th Symposium on VLSI Technology, VLSIT 2014 - Honolulu, United States Duration: 9 Jun 2014 → 12 Jun 2014

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)	0743-1562

Conference

Conference	34th Symposium on VLSI Technology, VLSIT 2014
Country/Territory	United States
City	Honolulu
Period	9/06/14 → 12/06/14

Access to Document

10.1109/VLSIT.2014.6894385

Cite this

Park, J. K., Kim, S. Y., Lee, K. H., Pyi, S. H., Lee, S. H., & Cho, B. J. (2014). Surface-controlled ultrathin (2 nm) Poly-Si channel junctionless FET towards 3D NAND flash memory applications. In Digest of Technical Papers - Symposium on VLSI Technology Article 6894385 (Digest of Technical Papers - Symposium on VLSI Technology). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIT.2014.6894385

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title = "Surface-controlled ultrathin (2 nm) Poly-Si channel junctionless FET towards 3D NAND flash memory applications",

abstract = "An ultrathin junctionless (JL) charge trap flash (CTF) thin-film transistor (TFT) with a sub-2 nm thick poly-Si channel is demonstrated for 3D stacked flash memory. It provides the excellent memory performance of faster program/erase (P/E) speed, larger memory window (>12 V), and better endurance (>104 cycles) than inversion-mode (IM) devices; this device also has excellent 10-year data retention at 150 °C, as well as improved on/off current ratio (>108) and subthreshold swing (SS). The transfer characteristics and the memory performance as a function of the poly-Si channel thickness (TCh) are also systematically investigated.",

author = "Park, {Jong Kyung} and Kim, {Seung Yoon} and Lee, {Ki Hong} and Pyi, {Seung Ho} and Lee, {Seok Hee} and Cho, {Byung Jin}",

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Park, JK, Kim, SY, Lee, KH, Pyi, SH, Lee, SH & Cho, BJ 2014, Surface-controlled ultrathin (2 nm) Poly-Si channel junctionless FET towards 3D NAND flash memory applications. in Digest of Technical Papers - Symposium on VLSI Technology., 6894385, Digest of Technical Papers - Symposium on VLSI Technology, Institute of Electrical and Electronics Engineers Inc., 34th Symposium on VLSI Technology, VLSIT 2014, Honolulu, United States, 9/06/14. https://doi.org/10.1109/VLSIT.2014.6894385

Surface-controlled ultrathin (2 nm) Poly-Si channel junctionless FET towards 3D NAND flash memory applications. / Park, Jong Kyung; Kim, Seung Yoon; Lee, Ki Hong et al.
Digest of Technical Papers - Symposium on VLSI Technology. Institute of Electrical and Electronics Engineers Inc., 2014. 6894385 (Digest of Technical Papers - Symposium on VLSI Technology).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - An ultrathin junctionless (JL) charge trap flash (CTF) thin-film transistor (TFT) with a sub-2 nm thick poly-Si channel is demonstrated for 3D stacked flash memory. It provides the excellent memory performance of faster program/erase (P/E) speed, larger memory window (>12 V), and better endurance (>104 cycles) than inversion-mode (IM) devices; this device also has excellent 10-year data retention at 150 °C, as well as improved on/off current ratio (>108) and subthreshold swing (SS). The transfer characteristics and the memory performance as a function of the poly-Si channel thickness (TCh) are also systematically investigated.

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Park JK, Kim SY, Lee KH, Pyi SH, Lee SH, Cho BJ. Surface-controlled ultrathin (2 nm) Poly-Si channel junctionless FET towards 3D NAND flash memory applications. In Digest of Technical Papers - Symposium on VLSI Technology. Institute of Electrical and Electronics Engineers Inc. 2014. 6894385. (Digest of Technical Papers - Symposium on VLSI Technology). doi: 10.1109/VLSIT.2014.6894385

Surface-controlled ultrathin (2 nm) Poly-Si channel junctionless FET towards 3D NAND flash memory applications

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