Survey of CPU and memory simulators in computer architecture: A comprehensive analysis including compiler integration and emerging technology applications

In computer architecture studies, simulators are crucial for design verification, reducing research and development time and ensuring the high accuracy of verification results. Several studies have developed and employed a verification environment by designing a custom in-house simulator that verifies the performance improvement of the proposed architecture for each research purpose by integrating multiple simulators or modifying existing ones. Recent advancements in deep neural networks and increased computational complexity have prompted research into emerging technologies, such as GPUs, processing-in-memory (PIM), and neural processing units (NPUs). Recently, custom in-house simulators were developed and actively employed for performance verification. However, constructing proper custom in-house simulators requires a greater grasp of the support functions and characteristics of current architectural simulators, which constitute the backbone of simulator creation. To meet these criteria, a comprehensive comparative analysis was conducted by examining the structures and output metrics supported across various architecture simulators, including representative CPU and memory simulators. Furthermore, it analyzes actual case studies of in-house simulators developed in recent emerging technology research ( i.e., GPUs, NPUs, PIM). Additionally, we examine the characteristics of compilers that support optimization for various recent workloads and simulators by analyzing case studies in which the integration of simulators and compilers has contributed to optimizing the overall simulator operations. Analyzing the overall verification process using these simulators, comparing each component, and confirming actual cases can provide essential insights for selecting and developing simulators suitable for computer architecture research. Consequently, this study contributes to maximizing the accuracy and efficiency of computer architecture research.