Symmetric varactor in 130-nm CMOS for frequency multiplier applications

Dongha Shim, K. O. Kenneth

Research output: Contribution to journalArticlepeer-review

25 Scopus citations

Abstract

A symmetric varactor (SVAR) in 130-nm digital complementary metaloxidesemiconductor (CMOS) for frequency multiplier applications with the maximum cutoff frequency of ∼ 320 GHz and a dynamic cutoff frequency of ∼ 125 GHz is demonstrated. To demonstrate the generation of odd-order harmonics and suppression of even-order ones, an SVAR was measured at the pumping frequency of 900 MHz. The measured third-order harmonic power is more than 25 dB higher than that for the second order. Harmonic balance simulations showed that the SVAR pumped by a 50-GHz signal source can generate a 150-GHz third-harmonic output signal with 15.8-dB minimum conversion loss at the input power of 7.8 dBm. The SVAR can be integrated with other (CMOS) components to generate millimeter-wave signals.

Original languageEnglish
Article number5725160
Pages (from-to)470-472
Number of pages3
JournalIEEE Electron Device Letters
Volume32
Issue number4
DOIs
StatePublished - Apr 2011

Keywords

  • Accumulation mode
  • complementary metal-oxide-semiconductor (CMOS)
  • frequency multiplier
  • millimeter wave
  • symmetric varactor (SVAR)

Fingerprint

Dive into the research topics of 'Symmetric varactor in 130-nm CMOS for frequency multiplier applications'. Together they form a unique fingerprint.

Cite this