System-level simulation of hardware spiking neural network based on synaptic transistors and if neuron circuits

We perform a system-level simulation of hardware spiking neural network (SNN) consisting of silicon-based synaptic transistors and integrate-and-fire (IF) neuron circuits. Using electrical models of the synaptic device and IF neuron circuit, a three-layer fully connected SNN in hardware is presented for MNIST pattern recognition by means of ex situ training. Right-justified rate coding is employed as an information encoding method, and negative weight values are implemented by a pair of the synaptic transistors (specifically, excitatory and inhibitory synapses). Furthermore, the variability effect occurring in the devices and circuits is demonstrated. This result indicates that the system has tolerance to the variations and how precisely the variations need to be controlled for hardware SNN applications.