TY - JOUR
T1 - Tunable Non-Volatile Gate-to-Source/Drain Capacitance of FeFET for Capacitive Synapse
AU - Kim, Tae Hyeon
AU - Phadke, Omkar
AU - Luo, Yuan Chun
AU - Mulaosmanovic, Halid
AU - Mueller, Johannes
AU - Duenkel, Stefan
AU - Beyer, Sven
AU - Khan, Asif Islam
AU - Datta, Suman
AU - Yu, Shimeng
N1 - Publisher Copyright:
© 1980-2012 IEEE.
PY - 2023/10/1
Y1 - 2023/10/1
N2 - Using 'capacitive' crossbar arrays for compute-in-memory (CIM) offers higher energy efficiency compared to 'resistive' crossbar arrays. The non-volatile capacitive (nvCap) synapse has been recently reported in MFM and MFS stacks with asymmetric electrode interfaces. In this work, a foundry FeFET is leveraged as the capacitive synapse for the first time, where the tunable gate-to-drain and gate-to-source capacitances (Cgd and Cgs) are exploited as the capacitive memory states. High capacitance on/off ratio (25) is obtained by relatively low program/erase voltages (±3.5V). Furthermore, it is demonstrated by TCAD simulation that the physical origins of on-state and off-state capacitance are dominated by the inversion capacitance and the overlap capacitance, respectively. Based on these results, design guidelines are presented to further increase the on/off ratio.
AB - Using 'capacitive' crossbar arrays for compute-in-memory (CIM) offers higher energy efficiency compared to 'resistive' crossbar arrays. The non-volatile capacitive (nvCap) synapse has been recently reported in MFM and MFS stacks with asymmetric electrode interfaces. In this work, a foundry FeFET is leveraged as the capacitive synapse for the first time, where the tunable gate-to-drain and gate-to-source capacitances (Cgd and Cgs) are exploited as the capacitive memory states. High capacitance on/off ratio (25) is obtained by relatively low program/erase voltages (±3.5V). Furthermore, it is demonstrated by TCAD simulation that the physical origins of on-state and off-state capacitance are dominated by the inversion capacitance and the overlap capacitance, respectively. Based on these results, design guidelines are presented to further increase the on/off ratio.
KW - compute-in-memory
KW - ferroelectric field-effect transistor
KW - Non-volatile capacitive synapse
UR - https://www.scopus.com/pages/publications/85169690882
U2 - 10.1109/LED.2023.3311344
DO - 10.1109/LED.2023.3311344
M3 - Article
AN - SCOPUS:85169690882
SN - 0741-3106
VL - 44
SP - 1628
EP - 1631
JO - IEEE Electron Device Letters
JF - IEEE Electron Device Letters
IS - 10
ER -
