Twin 2T0C DRAM Cells with Underlapped Gate-All-Around Write Transistor

Conventional two-transistor-zero-capacitor (2T0C) dynamic random access memory (DRAM) cells have the typical problems of low integration and short retention time. To address these drawbacks, most previous studies have utilized oxide-based transistors. However, this paper proposes a silicon-based 2T0C DRAM 2bit/cell structure, which preserves the advantages of both silicon-based semiconductors and 2T0C DRAM, while enhancing cell integration density and improving retention characteristics. Technology computer aided design (TCAD) simulation shows 107.41% improvement in retention characteristics via the asymmetric underlapped write transistor (WTr). Even though the number of terminals in 2T0C is doubled, the newly proposed shared read bit line (RBL) structure has 6 F² of unit cell size, which is the same as the existing 1T1C DRAM.