Unveiling Parasitic Capacitance Effects and Introducing Buried Structure for Enhanced RF Performance in 2-D Channel Devices

We conducted a comprehensive analysis of the factors affecting the analog performance of 2-D semiconductor devices using graphene. To address the challenges posed by parasitic capacitance effects in the top-gate graphene FET, we introduced a novel Buried structure with source/drain electrodes embedded. Through experimental verification, we observed significant performance improvements compared to the conventional structure. These research findings provide valuable insights into the limitations imposed by device structures on semiconductor device performance and offer promising avenues for future advancements. The proposed Buried structure presents a promising solution for optimizing device performance in various semiconductor device structure research endeavors. By leveraging this innovative approach, researchers can enhance the performance of graphene-based electronics for a wide range of high-speed applications.