Wafer scale encapsulation of MEMS devices

Woo Tae Park, Junghwa Cho, Holden Li, Thomas W. Kenny, Rob N. Candler, Huimou J. Li, Aaron Partridge, Gary Yama, Markus Lutz

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations

Abstract

MEMS packaging has always been a field of great importance since it can dominate the cost and size of a final working device. Considering this, we have concentrated on developing a wafer-scale encapsulation scheme which uses a thick epi-poly (epitaxially deposited poly silicon) layer as the sealing layer. This approach allows the use of conventional post processing, such as dicing, wire bonding, and other standard handling and mounting techniques. We also can minimize the chip area used for packaging, in some cases reducing the chip size by x5 from what was required for silicon fusion bonded covers. This packaging scheme can be used for various MEMS devices and can be integrated with other electronics. This paper will discuss the packaging process and show some preliminary results.

Original languageEnglish
Title of host publicationAdvances in Electronic Packaging 2003
Subtitle of host publicationVolume 1
PublisherAmerican Society of Mechanical Engineers
Pages209-212
Number of pages4
ISBN (Print)0791836908, 9780791836903
DOIs
StatePublished - 2003
Event2003 International Electronic Packaging Technical Conference and Exhibition - Haui, HI, United States
Duration: 6 Jul 200311 Jul 2003

Publication series

NameAdvances in Electronic Packaging
Volume1

Conference

Conference2003 International Electronic Packaging Technical Conference and Exhibition
Country/TerritoryUnited States
CityHaui, HI
Period6/07/0311/07/03

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