Wafer warpage analysis of stacked wafers for 3D integration

The demand for wafer stacking technology has been increasing significantly. Although many technical challenges of wafer stacking have improved greatly, there are still many processing issues to be resolved. One of them is wafer warpage since it causes process and product failures such as delamination, cracking, mechanical stresses, and even electrical failure. In this study the warpage of multi-stacked wafers has been evaluated. Three Si wafers have been stacked on a Si substrate using a thermo-compression Cu bonding. Each wafer stack was ground down to ∼30 μm and the thickness of the thinned Si wafer and wafer curvature were measured by FTIR (Fourier Transform Infrared Spectrometer) and FSM (Film-Stress Measurement), respectively. Wafer curvature becomes severe as the number of wafers in a stack increases, but the increment of wafer bow is reduced as the number of stack increases. The experimental results were also compared with the analytical model.