Work function optimization of dual metal buried channel array transistor dynamic random-access memory for simultaneous mitigation of gate-induced drain leakage, gate-induced junction leakage, pass gate effect, and 1‑row disturb

As dynamic random-access memory (DRAM) scaling continues, performance and integration density have improved, while reliability challenges have become increasingly critical. Various leakage and disturbance mechanisms, including gate-induced drain leakage (GIDL), gate-induced junction leakage (GIJL), pass gate effect (PGE), and 1-row disturb (1-RD), degrade data retention and stability. To mitigate gate-induced drain leakage (GIDL), a dual work function (DWF) structure that modulates the top metal work function has been introduced. However, the bottom metal work function also significantly influences other leakage mechanisms, highlighting the need for simultaneous optimization of both electrodes. In this study, the impacts of independently engineering the top and bottom metal work functions on these leakage mechanisms were analyzed. Simulation results demonstrate that overall leakage was effectively reduced compared with conventional single work function structures. These findings demonstrate the potential of DWF engineering to enhance DRAM reliability and provide practical design insights for future high-density memory technologies.